1. Field of the Invention
This invention relates to a data processing apparatus having a memory control function which is based on detecting the state of the CPU, and more particularly, to a data processing apparatus having a memory control function, provided in a system having an image memory such as the terminal of a VIDEOTEX system or a teletext receiver, for efficiently controlling data transfer between a CPU and the image memory.
2. Description of the Related Art
As is well known, in a system such as a terminal of a VIDEOTEX system or a teletext receiver in which transferred image data is displayed on a monitor CRT, an image memory is required for storing the image data through a CPU. In this case, the following three techniques may be made as an access scheme for the CPU to access the image data from the image memory.
(1) The CPU discriminates a display period--i.e. a period during which image data is displayed on the CRT--from a non-display period and accesses data from the image memory only during the non-display period.
(2) A display controller (e.g., a display control IC) controls all the operations of the image memory. When the CPU accesses data in the image memory, it transfers the address of the requested data and the data itself to the display controller in a port transfer system (e.g., a register). When the display controller detects transfer of the data from the CPU, it transfers the data to the image memory using an access period assigned in the display period by a work RAM.
(3) A read period, during which data in the image memory is read out to be displayed on the CRT, and an access period, during which the CPU accesses data from the image memory, are provided on a time-divisional basis. When the CPU accesses data from the image memory in the read period for display, a wait signal is output to the CPU at a suitable timing, thereby delaying access of the CPU until a possible maximum access period.
According to above technique (1), the CPU can access data from the image memory in only the non-display period, resulting in very poor data transfer efficiency. Since, according to technique (2), data can also be transferred during the non-display period by means of cycle stealing, the data transfer efficiency is relatively good. However, if an interruption or the like occurs while the CPU is transferring data to the image memory, a transfer address for the image data may be undesirably changed because data transfer is performed by the port transfer system. In order to eliminate this, management of transfer addresses in interruption processing or the like performed by the work RAM must be complicated. Therefore, extra memory address areas must be provided, and software is overloaded, with the result that data transfer efficiency is degraded. Since, according to technique (3), the CPU itself transfers data to the image memory, management of the transfer addresses in the interruption processing or the like can be easily performed. Since the time required for the CPU to access data in the image memory is generally longer than that required for the display controller to read out data from the image memory, a sufficient time margin is required for generating the wait signal at a proper timing. Therefore, if technique (3), which consumes much time for one access operation is adopted in a system such as the VIDEOTEX system or the teletext receiver in which a large amount of data is read out for display and at the same time written in the image memory, the data transfer efficiency is degraded.
Briefly, as a scheme for the CPU to access data from the image memory, technique (1) degrades the transfer efficiency, and technique (2) requires extra memory address areas and increases a burden on software. In addition, technique (3) degrades the data transfer efficiency when it is adopted in the VIDEOTEX system or the like wherein a large amount of data is read out and written in at a high speed.